Siavash Bayat-Sarmadi

Associate Professor

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Office:

Room 723

Computer Engineering Dept.

Sharif Univ. of Technology

Azadi Ave., Tehran, Iran

 

Lab:

Smart and Secure Systems (3S)

Room 504

Computer Engineering Dept.

 

Email: sbayat AT sharif.edu

Phone: (98) (21) 6616-6614

Fax:     (98) (21) 6601-9246


I am an associate professor with the department of Computer Engineering at Sharif University of Technology. I obtained my B.Sc. in Computer Hardware from University of Tehran in 2000, my M.Sc. in Computer Architecture from Sharif University of Technology in 2002 and my Ph.D. in Computer Hardware from University of Waterloo, Waterloo, Canada, in 2007. Before joining Sharif University, I was at industry in Toronto, Canada, for over 6 years (mainly at Advance Micro Devices (AMD)).

Research Interests:

·       Mobile Data Networks

·       Cyber Physical Systems/Internet of Things

o   Efficient, Dependable and Secure Architectures

·       ML/DL Acceleration

·       Privacy Preserving ML

o   2PC/MPC

·       Hardware Security and Trust

·       Cryptographic Computations

Courses:

Mobile Data Network [F21][S22][F23]

Digital Logic Design [F13][S14][F14][S15][S16][S17][S18][S19][S23]
Computer Organization [F13]

Digital System Design [F15][F16][F17][F18][F19][F21][F22][F23]

Hardware Security and Trust [F13][S14][F14][S15][F15][S17][S18][S19][S20][S21][F22]

Cryptographic Computations [F13][S14][F14][S15][S16][F16][F17][F18][F19][F20]

 

Patent:

·       Siavash Bayat-Sarmadi, Shahriar Ebrahimi, “Biometric authentication based on learning parity with noise”, US Patent App. 17/893,663, 2022.

·       Siavash Bayat-Sarmadi, Shahriar Ebrahimi, Hatameh Mosanaei Boorani, “Quantum-resistant cryptoprocessing”, US Patent 11,228,432, 2022

Publications:

·       F. Taheri, S. Bayat-Sarmadi, H. Rastaghi, “PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing”, to appear in IEEE Internet of Things Journal, 2023.

·       F. Taheri, S. Bayat Sarmadi, “MISC: Multi-Input Secure Two-Party Computation”, ISC International Journal of Information Security (ISeCure), 15(2), pp. 163-177, July 2023.

·       F. Taheri, S. Bayat-Sarmadi, S. Hadayeghparast, “RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference”, IEEE Internet of Things Journal, 9(23), pp. 24030-24037, December 2022.

·       S. Hadayeghparast, S. Bayat-Sarmadi, S. Ebrahimi, “High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT”, IEEE Internet of Things Journal, 9(17), pp. 15839 - 15846, September 2022.

·       F. Taheri, S. Bayat-Sarmadi, S. Ebrahimi, “Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), pp. 1231-1239, March 2022.

·       M.H. Farzam, S. Bayat-Sarmadi, H. Mosannaei-Boorani, Armin Alivand, “Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier”, IEEE Transactions on Circuits and Systems I: Regular Papers, 69(3), pp. 1221-1230, March 2022.

·       M.E. Mazaheri, S. Bayat Sarmadi, and F. Taheri-Ardakani, “A Study of Timing Side-Channel Attacks and Countermeasures on JavaScript and WebAssembly”, ISeCure, 14(1), pp. 27-46, Winter and Spring 2022.

·       S. Ebrahimi, S. Bayat-Sarmadi, “A Lightweight Fuzzy Extractor Based on LPN Problem for Device and Biometric Authentication in IoT”, IEEE Internet of Things Journal, 8(13), pp. 10706-10713, July 2021.

·       M. Salehi, S. Bayat-Sarmadi, “PLCDefender: Improving Remote Attestation Techniques for PLCs using Physical Model”, IEEE Internet of Things Journal, 8(9), pp. 7372-7379, May 2021.

·       M.H. Farzam, S. Bayat-Sarmadi, H. Mosannaei-Boorani, Armin Alivand, “Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier”, IEEE Transactions on Circuits and Systems I: Regular Papers, 68(5), pp. 2042-2050, March. 2021.

·       N. Shekofte, S. Bayat-Sarmadi, H. Mosannaei-Boorani, “A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration”, ISC International Journal of Information Security (ISeCure), 13(1), pp. 29-45, 2021.

·       M.H. Farzam, S. Bayat-Sarmadi, H. Mosannaei-Boorani, “Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key EncapsulationUsing an Efficient Scheduling”, IEEE Transactions on Circuits and Systems I: Regular Papers, 67(12), pp. 4895-4903, Dec. 2020.

·       S. Ebrahimi, S. Bayat-Sarmadi, “Lightweight and DPA-Resistant Post-Quantum Cryptoprocessor based on Binary Ring-LWE”, 20th International Symposium on Computer Architecture & Digital Systems, Guilan, August 2020.

·       M. Erfan Mazaheri, F. Taheri, S. Bayat Sarmadi, “Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly”, International ISC Conference on Information Security and Cryptology (ISCISC), 2020.

·       S. Ebrahimi, S. Bayat-Sarmadi, “Lightweight and Fault Resilient Implementations of Binary Ring-LWE for IoT Devices”, IEEE Internet of Things Journal, 7(8), pp. 6970 – 6978, Aug. 2020.

·       S. Ebrahimi, S. Bayat-Sarmadi, “Lightweight and DPA-Resistant Post-Quantum Cryptoprocessor based on Binary Ring-LWE”, 20th International Symposium on Computer Architecture & Digital Systems, 2020.

·       Raziyeh Salarifard and Siavash Bayat-Sarmadi, “An Efficient Low-Latency Point-Multiplication Over Curve25519”, IEEE Transactions on Circuits and Systems I: Regular Papers, 66(10), pp. 3854-3862, Oct 2019.

·       M.S. Sadeghi, S. Bayat-Sarmadi, S. Hessabi, “Towards On-Chip Network Security Using Runtime Isolation Mapping”, ACM Transactions on Architecture and Code Optimization, 16(3), August 2019.

·       S. Ebrahimi, S. Bayat-Sarmadi, H. Mosannaei-Boorani, “Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT”, IEEE Internet of Things Journal, 6(3), pp 5500-5507, June 2019.

·       O. Ranjbar, S. Bayat-Sarmadi, F. Pooyan, H. Asadi, “A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs”, Journal of Electronic Testing: Theory and Applications (JETTA), 35(2), pp 201-214, April 2019.

·       Taha Shaahroodi, Siavash Bayat-Sarmadi, Hatameh Mosanaei-Boorani, “Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain over GF(2m)”, IEEE Transactions on Circuits and Systems I: Regular Papers, 66(4), April 2019.

·       Mehran Mozaffari Kermani, Siavash Bayat-Sarmadi, and Reza Azarderakhsh, “High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE”, IEEE LASCAS, Columbia, Feb 2019.

·       Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Hatameh Mosanaei-Boorani, “A Low-Latency and Low-Complexity Point-Multiplication in ECC”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2869-2877, Sept. 2018.

·       A. Boorghany, S. Bayat-Sarmadi, R. Jalili, “Practical Provably-Secure Authenticated Encryption Schemes Using Lattice-based Pseudorandom Function SPRING”, Scientia Iranica Journal D, 25(6), pp 3442-3460, 2018.

·       Marzieh AshrafiAmiri, Amir Hosein Afandizadeh Zargari, Seyed Mohammad-Hossein Farzam, Siavash Bayat-Sarmadi, “Towards Side Channel Secure Cyber-Physical Systems”, the CSI International Symposium on Real-Time and Embedded Systems and Technologies (RTEST), 2018.

·       Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi, “Reliable hardware architectures for efficient secure hash functions ECHO and fugue”, 204-207, CF 2018.

·       Mohammad-Hossein Yalame, Mohammad-Hossein Farzam, Siavash Bayat-Sarmadi, “Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer”, International Conference on Applications and Technologies in Information Security (ATIS), 2017.

·       Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Mohammad Farmani, “High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases”, IEEE Transactions on Circuit and Systems I, 63(11), Nov. 2016.

·       Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat-Sarmadi, and Chiou-Yng Lee, “Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications”, IEEE Transactions on VLSI Systems, vol.23, no.9, pp.1969,1972, Sept. 2015.

·       B. Khaleghi, A. Ahari, H. Asadi, S. Bayat-Sarmadi, “FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic”, IEEE Embedded Systems Letters, 7(2): 46-50, June 2015.

·       A. Boorghany, S. Bayat-Sarmadi, R. Jalili, “On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards”, ACM Transactions on Embedded Computing Systems (SI: Embedded Platforms for Cryptography in the Coming Decade), 14(3), Article 42, 25 pages, April 2015.

·       S. Bayat-Sarmadi, M. Farmani, “High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2^m) based on Trinomials”, IEEE Transactions on Circuits and Systems II, 62(4): 377-381, January 2015.

·       M. Mozaffari Kermani, K. Tian, R. Azarderakhsh, S. Bayat Sarmadi, "Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems," IEEE Embedded Systems Letters, 6(4): 89-92, October 2014.

·       S. Bayat-Sarmadi, M. Mozaffari-Kermani, A. Reyhani-Masoleh, “Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7):1105-1109, July 2014

·       Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, and Siavash Bayat-Sarmadi, “Reliable Concurrent Error Detection Architectures for Extended Euclidean-based Division over GF(2m)”, IEEE Transactions on VLSI Systems, 22(5):995-1003, May 2014

·       S. Bayat-Sarmadi, M. Mozaffari-Kermani, Reza Azarderakhsh, and Chiou-Yng Lee, “A Dual Basis Super-Serial Multiplier Suitable for Lightweight Cryptographic Applications, IEEE Transactions on Circuits and Systems II, 61(2):125-129, Feb 2014

·       S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection in Finite Field Arithmetic Operations using Pipelined and Systolic Architectures”, IEEE Transactions on Computers,58(11): 1553-1567, Nov. 2009

·       S. Bayat-Sarmadi and M. A. Hasan, “Detecting Errors in a Polynomial Basis Multiplier Using Multiple Parity Bits for Both Inputs”,  in proceeding of the 25th IEEE International Conference on Computer Design (ICCD), 2007

·       S. Bayat-Sarmadi and M. A. Hasan, “Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes”, in proceeding of the 18th IEEE International ASAP Conference, 2007

·       S. Bayat-Sarmadi and M. A. Hasan, “On Concurrent Detection of Errors in Polynomial Basis Multiplication”, IEEE Transactions on VLSI Systems, 15(4):413-426, April 2007

·       S. Bayat-Sarmadi, “Timing Analysis of the Solutions of the Discrete-Time Wiener-Hopf Equations”, in  proceeding of  the International Conference for Upcoming Engineers (ICUE), 2006

·       S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme”, in proceeding of  the IEEE International Symposium on Defect and fault Tolerance in VLSI Systems (DFT), 2005

·       A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Bayat-Sarmadi, “A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation”, in proceeding of the IEEE International Conference on Dependable Systems and Networks (DSN), 2003

·        S. Bayat-Sarmadi, M. Röser, and D.  Tavangarian, “Metadata as a Basis for Automatic Generation of Learning Documents”, in proceeding of the Workshop on Interactive Computer Aided Learning - Learning Objects & Reusability of Content (ICL) 2003

·        S.G. Miremadi, S. Bayat-Sarmadi, and G. Asadi, “Speedup Analysis in Simulation-Emulation Co-Operation”, in proceeding of the IEEE International Conference on Field programmable Technology (FPT), 2002

·        S. Bayat-Sarmadi, S.G. Miremadi, G. Asadi, and A. R. Ejlali, “Fast Prototyping with Co-Operation of Simulation and Emulation”, in proceeding of the 12th International Conference on Field Programmable Logic and Applications (FPL), 2002

·        S. Hessabi, A. Ahmadinia, G. Asadi, S. Bayat-Sarmadi , and M. Gudarzi, “Co-FFT Design: FFT Implementation on CSoC”, in proceedings of IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (A&QT-R), 2002.

·        G. Asadi, S.G. Miremadi, S. Bayat Sarmadi, and A. Ejlali , “Speeding up Design Verification Using Co-Operation of Simulation and Emulation”,  in the proceeding of the IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (AQTR), 2002.

 

مقالات فارسی:

·       امیر میرزایی، محمد حسین فرزام، سیاوش بیات‌سرمدی، «ارائه مدل عملی حفظ حریم خصوصی در قراردادهای هوشمند مبتنی بر زنجیره بلوکی با کاهش سربار»، شانزدهمین کنفرانس بین‌المللی انجمن رمز ایران، مشهد، ۱۳۹۸.

·       رضا روح‌قلندری، حاتمه مثنایی‌بورانی و سیاوش بیات‌سرمدی، « مروری بر عملیات معکوس در میدان‌های متناهی دودویی و اول»، نشریه مهندسی برق و کامپیوتر ایران، ب-مهندسی کامپیوتر، سال ۱۷، شماره ۲، تابستان ۱۳۹۸.

·       فاطمه پویان و سیاوش بیات‌سرمدی، « بررسی روش های مقابله با حملات کانال جانبی از طریق منطق تفاضلی پویا»، نشریه پدافند الکترونیکی و سایبری، ۱۳۹۸.

·       پریسا حسنی‌زاده، سیاوش بیات سرمدی, «امنیت در پردازش لبه‌ای: مروری بر چالش‌ها و راهکارهای موجود» نشریه علوم رایانش و فناوری اطلاعات, ۱۳۹۸.

·       پریسا حسنی‌زاده، خالد دغلاوی، محمد حسین فرزام، علی رسایی، سیاوش بیات سرمدی, "ﻧﮕﺎﻫﻲ ﺑﺮ ﭘﺮدازش ﻟﺒﻪ: ﻣﺰاﻳﺎ، ﭼﺎﻟﺶ‌ها و اﻣﻨﻴت" بیست و سومین کنفرانس ملی سالانه انجمن کامپیوتر ایران, تهران, ۱۳۹۶.