Journal Articles by A. A. Mazreah

A. A. Mazreah and M. T. M. Shalmani
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, 46(4), 413-426, 2013
A. A. Mazreah and M. M. Shalmani
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal, 43(11), 766-792, 2012
A. A. Mazreah and M. T. M. Shalmani
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics journal, 42(11), 1187-1207, 2011
A. A. Mazreah, M. R. Sahebi, and M. T. M. Shalmani
A Novel Nano-Scaled SRAM Cell
International Journal of Electronics and Communication Engineering, 4(5), 781-783, 2010
A. A. Mazreah, M. N. Romani, M. T. Manzuri, and A. Mehrparvar
A low power and high density cache memory based on novel SRAM cell
IEICE Electronics Express, 6(15), 1084-1090, 2009
A. A. Mazreah, M. T. Manzuri, and A. Mehrparvar
A High Density and Low Power Cache Based on Novel SRAM Cell.
JCP, 4(7), 567-575, 2009
A. A. Mazreah, M. T. M. Shalmani, H. Barati, A. Barati, and A. Sarchami
A Low Power SRAM Base on Novel Word-Line Decoding
World Academy of Science, Engineering and Technology, 2(1), 149-153, 2008
A. A. Mazreah, M. T. M. Shalmani, H. Barati, and A. Barati
A novel four-transistor SRAM cell with low dynamic power consumption
International Journal of Electronics, Circuits and Systems (IJECS), 2(3), 144-148, 2008

Conference Papers

A. A. Mazreah, M. T. M. Shalmani, and A. Mehrparvar
A Nanoscale CMOS SRAM Cell for High Speed Applications
2009 Fifth International Conference on MEMS NANO, and Smart Systems, 2009
A. A. Mazreah and M. T. M. Shalmani
A Low Power SRAM Based on Five Transistors Cell
Computer Society of Iran Computer Conference, 2008
A. A. Mazreah, M. T. M. Shalmani, R. Noormandi, and A. Mehrparvar
A novel zero-aware read-static-noise-margin-free SRAM cell for high density and high speed cache application
2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
A. A. Mazreah, M. R. Sahebi, M. T. Manzuri, and S. J. Hosseini
A novel zero-aware four-transistor SRAM cell for high density and low power cache application
2008 International Conference on Advanced Computer Theory and Engineering, 2008