Computer Engineering Dept.
Sharif Univ. of Technology
Azadi Ave., Tehran, Iran
Email: sbayat AT sharif.edu
Phone: (98) (21) 6616-6614
Fax: (98) (21) 6601-9246
I am an assistant professor with the department of Computer Engineering at Sharif University of Technology. I obtained my B.Sc. in Computer Hardware from University of Tehran in 2000, my M.Sc. in Computer Architecture from Sharif University of Technology in 2002 and my Ph.D. in Computer Hardware from University of Waterloo, Waterloo, Canada, in 2007. Before joining Sharif University I was at industry in Toronto, Canada, for over 6 years (mainly at Advance Micro Devices (AMD)).
· Cyber Physical Systems/Internet of Things
o Efficient, Dependable and Secure Computing and Architectures
· Hardware Security and Trust
· Cryptographic Computations
Digital System Design [F15][F16]
Hardware Security and Trust [F13] [S14][F14][S15][F15][F16]
Computations [F13] [S14][F14][S15][S16][S17]
· Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Hatameh Mosanaei-Boorani, “A Low-Latency and Low-Complexity Point-Multiplication in ECC”, IEEE Transactions on Circuits and Systems I: Regular Papers, to appear, 2018.
· Yalame, Mohammad Hossein, Mohammad Hossein Farzam, and Siavash Bayat-Sarmadi, "Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer", International Conference on Applications and Techniques in Information Security. Springer, Singapore, 2017.
· Raziyeh Salarifard, Siavash Bayat-Sarmadi, and Mohammad Farmani, “High-Throughput Low-Complexity Unified Multipliers Over GF(2m) in Dual and Triangular Bases”, IEEE Transactions on Circuits and Systems I: Regular Papers 63(11), 1944-1953, 2016.
· Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat-Sarmadi, and Chiou-Yng Lee, “Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications”, IEEE Transactions on VLSI Systems, 23(9),1969-1972, Sept. 2015.
· B. Khaleghi, A. Ahari, H. Asadi, S. Bayat-Sarmadi, “FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic”, IEEE Embedded Systems Letters, 7(2): 46-50, June 2015.
· A. Boorghany, S. Bayat-Sarmadi, R. Jalili, “On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards”, ACM Transactions on Embedded Computing Systems (SI: Embedded Platforms for Cryptography in the Coming Decade), 14(3), Article 42, 25 pages, April 2015.
· S. Bayat-Sarmadi, M. Farmani, “High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2^m) based on Trinomials”, IEEE Transactions on Circuits and Systems II, 62(4): 377-381, January 2015.
· M. Mozaffari Kermani, K. Tian, R. Azarderakhsh, S. Bayat Sarmadi, "Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems," IEEE Embedded Systems Letters, 6(4): 89-92, October 2014.
· S. Bayat-Sarmadi, M. Mozaffari-Kermani, A. Reyhani-Masoleh, “Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7):1105-1109, July 2014
· Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, and Siavash Bayat-Sarmadi, “Reliable Concurrent Error Detection Architectures for Extended Euclidean-based Division over GF(2m)”, IEEE Transactions on VLSI Systems, 22(5):995-1003, May 2014
· S. Bayat-Sarmadi, M. Mozaffari-Kermani, Reza Azarderakhsh, and Chiou-Yng Lee, “A Dual Basis Super-Serial Multiplier Suitable for Lightweight Cryptographic Applications, IEEE Transactions on Circuits and Systems II, 61(2):125-129, Feb 2014
· S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection in Finite Field Arithmetic Operations using Pipelined and Systolic Architectures”, IEEE Transactions on Computers,58(11): 1553-1567, Nov. 2009
· S. Bayat-Sarmadi and M. A. Hasan, “Detecting Errors in a Polynomial Basis Multiplier Using Multiple Parity Bits for Both Inputs”, in proceeding of the 25th IEEE International Conference on Computer Design (ICCD), 2007
· S. Bayat-Sarmadi and M. A. Hasan, “Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes”, in proceeding of the 18th IEEE International ASAP Conference, 2007
· S. Bayat-Sarmadi and M. A. Hasan, “On Concurrent Detection of Errors in Polynomial Basis Multiplication”, IEEE Transactions on VLSI Systems, 15(4):413-426, April 2007
· S. Bayat-Sarmadi, “Timing Analysis of the Solutions of the Discrete-Time Wiener-Hopf Equations”, in proceeding of the International Conference for Upcoming Engineers (ICUE), 2006
· S. Bayat-Sarmadi and M. A. Hasan, “Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme”, in proceeding of the IEEE International Symposium on Defect and fault Tolerance in VLSI Systems (DFT), 2005
· A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, G. Asadi, and S. Bayat-Sarmadi, “A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation”, in proceeding of the IEEE International Conference on Dependable Systems and Networks (DSN), 2003
· S. Bayat-Sarmadi, M. Röser, and D. Tavangarian, “Metadata as a Basis for Automatic Generation of Learning Documents”, in proceeding of the Workshop on Interactive Computer Aided Learning - Learning Objects & Reusability of Content (ICL) 2003
· S. Bayat-Sarmadi, S.G. Miremadi, G. Asadi, and A. R. Ejlali, “Fast Prototyping with Co-Operation of Simulation and Emulation”, in proceeding of the 12th International Conference on Field Programmable Logic and Applications (FPL), 2002
· S. Hessabi, A. Ahmadinia, G. Asadi, S. Bayat-Sarmadi , and M. Gudarzi, “Co-FFT Design: FFT Implementation on CSoC”, in proceedings of IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (A&QT-R), 2002.
· G. Asadi, S.G. Miremadi, S. Bayat Sarmadi, and A. Ejlali , “Speeding up Design Verification Using Co-Operation of Simulation and Emulation”, in the proceeding of the IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics (AQTR), 2002.