Alireza Ejlali, Ph.D. 

    Assistant Professor

    Department of Computer Engineering Sharif University of Technology

    Email: my_last_name AT sharif.edu

 
 

 

     

   

Research Interests

Embedded Systems

Dependable Embedded Systems

Low Power Embedded Systems

 

Low Power Design

Power Consumption Issues in Fault Tolerant Systems

Power Consumption of On-Chip Communication

 

Dependability Evaluation and Reliability Assessment

Fault Injection into HDL Models (Simulation-Based and FPGA-Based)

Reliability Issues in Deep Sub-Micron VLSI

 

 

Publications

  1. A. Ejlali, B.M. Al-Hashimi, P. Rosinger, S.G. Miremadi, and L. Benini, "Performability/Energy Trade-off in Error-Control Schemes for On-Chip Networks", Accepted for publication in IEEE Transactions On Very Large Scale Integration (VLSI) Systems.

  2. A. Ejlali, and S.G. Miremadi, "Error Propagation Analysis Using FPGA-based SEU-Fault Injection", Accepted for publication in Microelectronics Reliability.

  3. A. Ejlali, and S.G. Miremadi, "Emulating Switch-Level models of CMOS Circuits", Microelectronic Engineering, Volume: 84, Issue: 2, pp. 204-212, February 2007.

  4. G. Asadi, S.G. Miremadi, and A. Ejlali,  "Fast Co-Verification of HDL Models", Microelectronic Engineering, Volume: 84, Issue: 2, pp. 218-228, February 2007.

  5. A. Ejlali, B.M. Al-Hashimi, M.T. Schmitz, P. Rosinger, and S.G. Miremadi, "Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume: 14, Issue: 4, pp. 323-335, April 2006.

  6. A. Ejlali, and S. G. Miremadi, "FPGA-Based Fault Injection into Switch-Level Models", Microprocessors and Microsystems, Vol. 28, Issue: 5-6, pp. 317-327, August 2004.

  7. A. Ejlali, and S. G. Miremadi, "FPGA-based Monte Carlo Simulation for Fault Tree Analysis", Microelectronics Reliability, Vol. 44, Issue: 6, pp. 1017-1028, June 2004.

  8. A. Ejlali, B.M. Al-Hashimi, P. Rosinger, and S.G. Miremadi, "Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks", in Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exhibition (DATE'07), pp. 1647-1652, Nice, France, April 2007. 

  9. M. Fazeli, A. Patooghy, S.G. Miremadi and A. Ejlali, "Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies", in Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-2007), pp. 276-285, Edinburgh, UK, June 2007.

  10. A. Ejlali, and B.M. Al-Hashimi, "SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks", in Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2008), pp.67-76, Newcastle, UK, 2008.

  11. M. Khatir, A. Moradi, A. Ejlali, M. T. Manzuri Shalmani, and M. Salmasizadeh, "A Secure and Low-Energy Logic Style Using Charge Recovery Approach", Accepted for publication in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2008), Bangalore, India, 2008.

  12. Y. Cai, M. Schmitz, A. Ejlali, B.M. Al-Hashimi, and S.M. Reddy, " Cache Size Selection for Performance, Energy and Reliability of Time-Constrained Systems", in Proceedings of 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), pp. 923-928, Yokohama, Japan 2006.

  13. A. Ejlali, M. Schmitz, B.M. Al-Hashimi, S.G. Miremadi, and P. Rosinger, "Energy Efficient SEU-Tolerance in DVS-Enabled Real-Time Systems through Information Redundancy", in Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2005), pp.281-286, San Diego, California, USA, 2005.

  14. G. Asadi, S.G. Miremadi, H.R. Zarandi, and A. Ejlali, "Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs", in Proceedings of the IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC 2004), pp. 327-332, Papeete, Tahiti, French Polynesia, March 2004.

  15. H.R. Zarandi, S.G. Miremadi, S. Hessabi, and A. Ejlali, "A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models", in Proceedings of International Conference on Embedded Systems and Applications (ESA 2004), pp. 582-588, USA, June 2004.

  16. A. Ejlali, and S.G. Miremadi, "Switch-Level Emulation", in Proceedings of the 40th ACM/IEEE Design Automation Conference (DAC-40), pp. 644-649, Anaheim, USA, June 2003.

  17. A. Ejlali, and S.G. Miremadi, "Time-to-Failure Tree", in Proceedings of the 49th IEEE Annual Reliability and Maintainability Symposium (RAMS 2003), pp. 148 -152, Florida, USA, January 2003.

  18. A. Ejlali and S.G. Miremadi, H. R. Zarandi, G. Asadi and S. B. Sarmadi, "A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation", in Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-2003), pp. 479-488, San Francisco, USA, June 2003.

  19. S.G. Miremadi, and A. Ejlali, "Switch-Level Fault Emulation", in Proceedings of the 13th International Conference on Field Programmable Logic and Application (Springer LNCS 2778) (FPL 2003), pp. 849-858, Lisbon, Portugal, 2003.

  20. S. Bayat Sarmadi, S.G. Miremadi, G. Asadi, and A. Ejlali, "Fast Prototyping with Co-operation of Simulation and Emulation", in Proceedings of 12th International Conference on Field Programmable Logic and Application (Springer LNCS 2438) (FPL 2002), pp. 15-25, Montpellier (La Grande-Motte), France, 2002.

  21. H.R. Zarandi, G. Miremadi, A. Ejlali, "Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models", in Proceedings of 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), pp. 485-492, Cambridge, MA, U.S.A, November 2003.

  22. H.R. Zarandi, G. Miremadi, and A. Ejlali, "Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems", in Proceedings of the International Symposium on Parallel and Distributed Computing (ISPDC 2003), pp. 281-287, Ljubljana, Slovenia, October 2003.

  23. G. Asadi, S.G. Miremadi, S. Bayat Sarmadi, and A. Ejlali, "Speeding up Design Verification Using Co-operation of Simulation and Emulation", in Proceedings of 2002 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics, pp. 283-288, Cluj-Napoca Romania, May 2002.

  24. H.R. Zarandi, S.G. Miremadi, and A. Ejlali, "SILVER: A Simulation-based Fault Injection Tool at Switch Level Using Verilog", in Proceedings of Joint 1st Int. Conference on Soft Computing and Intelligent Systems and 3rd Int. Symposium on Advanced Intelligent Systems (SCIS & ISIS 2002), Tsukuba, Japan, October 2002.

  25. G. Asadi, S.G. Miremadi, H.R. Zarandi, and A. Ejlali, "Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects", in Proceedings of the IEEE International Conference on Field programmable Technology (FPT 2003), pp.428-430, Tokyo, Japan, December 2003.

  26. A. Ejlali, B. M. Al-Hashimi, S.G. Miremadi, "Fast Observation Architecture for FPGA-based SEU Analysis", in Proceedings of European Test Symposium (ETS 2005), 2005.

  27. S. Timarchi, S.G. Miremadi, and A. Ejlali, "Evaluation of Some Exponential Random Number Generators Implemented by FPGA", in Proceedings of the International Conference on Parallel and Distributed Computing and Networks (PDCN 2005), pp. 578-583, Innsbruck, Austria, February 2005.

  28. S. Timarchi, S.G. Miremadi, A. Ejlali, "A Comparative Evaluation of Some Hardware-Based Pseudo-Random Number Generators", in Proceedings of 10th Annual Int. CSI Computer Conference (CSICC 2005), Iran, February 2005.

  29. S. Timarchi, S.G. Miremadi, A. Ejlali, "Evaluation of Some Exponential Random Number Generators", in Proceedings of 10th CSI Computer Conference (CSICC 2005), pp. 42-49, Iran, March 2005. [in Persian language]

  30. M. T. Manzoori, and A. Ejlali "Active Noise Control Using Adaptive Filters Based on Genetic Algorithm", in Proceedings of 7th CSI Computer Conference (CSICC 2002), pp. 554-561, Iran, March 2002. [in Persian language]

 

 

Courses Taught

Low Power Design, Grad.

Embedded System Design, Grad.

Digital System Design (CAD, FPGA, Verilog), Undergrad.

Logic Design, Undergrad.

Computer Architecture LAB.

Electronics LAB.

 

 

 

Last Update:  18 June 2008