Sharif University of Technology
School of Electrical Engineering
Azadi Avenue, Tehran, Iran

Office: 611, Electrical Engineering New Building
Phone: 6616-5928
Email: b_alizadeh@sharif.edu

• Ph.D. in Electrical and Computer Engineering, University of Tehran, Iran [1998-2004]

• VHDL and Verilog FPGA/ASIC Design

• System-level Design as well as Hardware/Software Co-design

• Logic Minimization and High Level Synthesis Algorithms (Resource Sharing, Scheduling and Binding)

• Switch Level Simulation Algorithms

• Formal Property Verification and Property Languages such as PSL

• Assertion-based Verification

• FPGA based Design and Implementation (Altera/Xilinx/Actel)

• Engineering Applications: Model Technology ModelSim EE (VHDL & Verilog); Altera MaxplusII and Quartus II; Synopsys Design Compiler/Analyzer/Prime Time; Exemplar Leonardo Spectrum, OrCAD and Cadence System Tools to do place and route some designs

• Verification Group Manager at Tehran University

• VLSI Group Manager in Emad Semicon Co.

• Senior Digital Designer in Emad Semicon Co.

• DSP Core and Applications at Tehran University

• PCB Designer in ITRC

• FPGA-based Digital IC Design Methodology, 1-day workshop at Sharif University of Technology, March 2006

• Digital IC Design Methodologies (ASIC and FPGA), 2-days workshop at AmirKabir University (14th Iranian Conference on Electrical Engineering ), May 2006

Books:

[1] "Fundamentals of Digital Circuit Design with Verilog", Sharif University Press, 2008

[2] "Fundamentals of Digital Circuit Design with VHDL", Sharif University Press, 2009

Papers:

[1] B. Alizadeh, M. Fujita, "A Unified Framework for Equivalence Verification of Datapath-oriented Applications", accepted by IEICE Transactions on INF. and SYST., Japan, 2009.

[2] O. Sarbishei, M. Tabandeh, B. Alizadeh, M. Fujita, "A Formal Approach for Debugging Arithmetic Circuits", accepted by IEEE Transactions on CAD (TCAD),  2009.

[3] B. Alizadeh, M. Fujita, "Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions", CFV08, Australia , 2008.

[4] O. Sarbishei, B. Alizadeh, M. Fujita, "Arithmetic Circuits Verification without Looking for Internal Equivalences", MEMOCODE08, USA,  2008.

[5] B. Alizadeh, M. Fujita, "Sequential Equivalence Checking using a Hybrid Boolean-word Level Decision Diagrams", CSICC  2008.

[6] B. Alizadeh, M. Fujita, "Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions", ATVA07, Japan, pp. 129-144, 2007.

[7] B. Alizadeh, M. Fujita, "A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers", HLDVT07, USA , 2007.

[8] B. Alizadeh, M. Fujita, "A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions", IWLS07, USA, pp. 298-304, 2007.

[9] B. Alizadeh, M. Fujita, "LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware/Software Co-designs", CFV07, Germany, pp. 15-29, 2007.

[10] B. Alizadeh, "Word Level Functional Coverage Computation", International Conference ASP-DAC 2006.

[11] A. Hooshmand, S. Shamshiri, M. Alisafaee, B. Alizadeh, P. Lotfikamran, M. Naderi and Z. Navabi, "Binary Taylor Diagrams: An Efficient Implementation of Taylor Expansion Diagrams", IEEE International Symposium on Circuits and Systems (ISCAS) 2005, Japan, pages 424-427.

[12] B. Alizadeh, Z. Navabi, "Word Level Symbolic Simulation in Processor Verification, IEE-Proceedings Computers and Digital Techniques Journal, Vol. 151, No. 5, September 2004, pages 356-366.

[13] B. Alizadeh, Z. Navabi, "CTL Property Checking based on a High Level Model, Iranian Journal of Electrical and Computer Engineering, Vol. 1, No. 2, 1382, pages 92-98.

[14] B. Alizadeh, Z. Navabi, "Property Checking Based on Hierarchical Integer Equations", IEEE International Conference on ACSD 2004, Canada, pages 26-35.

[15] B. Alizadeh, "Check High Level Properties in Arithmetic Circuits, WSEAS Transactions on Circuits and Systems, Issue 2, Vol. 3, April 2004, pages 373-378.

[16] B. Alizadeh, Z. Navabi, "Using Integer Equations to Check PSL Properties in RT Level Design", 4th International Workshop on IWSOC 2004, Canada, pages 83-86.

[17] B. Alizadeh, M.R. Kakoee, Z. Navabi, "A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment, WSEAS Transactions on Circuits, Vol. 2, No. 1, January 2003, pages 36-41.

[18] B. Alizadeh, M.R. Kakoee, "Using Integer Equations for High Level Formal Verification Property Checking, ISQED03, San Jose, 2003, pages 69-74.

[19] B. Alizadeh, H.R. Hashempour, Z. Navabi, "A VHDL Based Integrated Environment for Reliable System Design", EuroCAD and NATW, 1998.

[20] B. Alizadeh, S.M. Fakhraei, Z. Navabi, ''Switch Level Simulation in VHDL", Computer Society Conference, Jan 1998.

[21] B. Alizadeh, Z. Navabi, "Component Modeling for Reliability by simulation " ,VIUF conference in Arizona, 1997.

• Digital Logic Design

• Microprocessor I

• Standard Computer Interface Circuits

• Embedded Systems Design

• Formal Verification

• ASIC/FPGA Chip Design