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Last updated on February 13, 2022 Just
for fun: Stupid
sort, The simplest sorting algorithm with only one loop… In 2000, when I was a
PhD student at Glasgow University, I published a note in the departmental newsletter (issue 599, 2 October 2000) on a simple
sort algorithm that had only one loop and called it Stupid Sort (you surely
know that sort algorithms are either recursive or non-recursive but with two
nested loops). Several years later, the algorithm has been reported as Gnome sort by Dr Dick Grune. It seems that the algorithm is getting more importance! Educational Background Dec.97-Oct.01 Ph.D. in Computing Science, Department of Computing
Science, University of Glasgow, Glasgow, U.K. (Thesis title: Performance
analysis of wormhole routing in multicomputer interconnection networks);
Graduated 1 March 2002. Jan.92-Jan.94 M.Sc. in Computer Engineering (Computer Architecture),
Department of Computer Engineering, Sharif University of Technology, Tehran,
Iran. (Thesis title: The design and implementation of a vector-signal
coprocessor for 8088 microprocessor). Sep.87-Sep.91 B.Sc. Computer Engineering (Computer Hardware),
Department of Electrical and Computer Engineering, Shahid-beheshti
University (former National University of Iran), Tehran, Iran. (Final
project: The design of a robot controller for solving Hanoi towers problem). Honors and Awards 2020 Distinguished book author of Sharif University of
Technology. 2018 Best paper award, CADS. 2017 Best paper award, NOCS. 2015 Distinguished book author of Sharif University of
Technology. 2014 Winner of Ministry of Communication and Information
Technology’s prize for contribution to IT research and education. 2013 Distinguished researcher of Sharif University of Technology. 2010 Distinguished researcher of Sharif University of
Technology. 2008 Distinguished researcher of Sharif University of
Technology. 2007 Distinguished researcher of Sharif University of
Technology. 2007 TWAS (Third World Academy of Sciences) prize winner of
young scientist in Engineering Sciences. 2006 Khwarizmi international award in Basic Sciences. 2005 Distinguished researcher of Iran (nominated by IPM). 2004 Distinguished researcher of Sharif University of
Technology. 2002 Ph.D. thesis nominated for 2001/2002 UK best Ph.D.
dissertations competition in Computer Science. 1996 The first-best applicant (considering exam and interview
results) in the Iranian national examination for receiving a bursary to do a
Ph.D. in Computing Science abroad. Professional Services and Membership Editor-in-Chief, Associate Editor and/or Editorial
Board Member of ·
IEEE Computer Architecture
Letters, 2020-Present. ·
ACM Computing Surveys,
2013-Present. ·
The CSI Journal on Computer Science & Engineering, 2006-2016. ·
IEEE
Transactions on Computers, IEEE Computer Society, 2011-2015. ·
International Journal of
Parallel and Distributed Computing and Networks, ACTA Press, 2011-Present. ·
Computers & Electrical
Engineering, Elsevier, 2010-2014, and 2016-Present. ·
International Journal of
Computers and Applications, ACTA Press, 2006-Present. ·
The CSI Journal on
Computer Science and Engineering, CSI Press, 2005-Present. Member of·
ACM (1998-Present), ·
Computer Society of Iran (2003- Present), ·
Informatic Society of Iran (2003- Present). Work Experience ·
Visiting Professor, National University of
Singapore, Singapore. Mar. 21-Sep.21 ·
Visiting Professor, JKU-Linz, Jul-Dec 2018. ·
Visiting Professor, NUS School of Computing,
Singapore. Jan-Jun 2018. ·
Professor, Sharif University of Technology,
Iran. Sep 2010-Present. ·
Visiting Professor, University of
Franche-Comte, Montbeliard, France. Jun-Aug 2012. ·
Visiting Professor, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland. Sep 2009-Aug 2010. ·
Head of Hardware Group, Sharif University of
Technology, Iran. Sep 2008-Aug 2009. ·
Vice-chair of Graduate Studies, Department of
Computer Engineering, Sharif University of Technology, Iran. Sep 2006-Sep
2008. ·
Associate Professor, Sharif University of Technology,
Iran. Sep 2005-Aug 2010. ·
Tenured Faculty Member, Sharif University of
Technology, Iran. Sep 2005-Present. ·
Head, School of Computer Science, Institute for
Research in Fundamental Sciences (former Institute for Studies in Theoretical
Physics and Mathematics, IPM), Iran. Jan 2003-Present. ·
Assistant Professor, Sharif University of
Technology, Iran. Sep 2002-Aug 2005. ·
Post-doctoral Research Assistant, University of
Glasgow, U.K. Jul 2001-May 2002. ·
Associate lecturer (part-time), University of
Glasgow, U.K. Oct 2000-Jun 2001. Research Interests ·
Advanced computer architecture, ·
Learning architectures, ·
Memory system architectures, ·
Next generation storage systems, ·
Systems-on-Chip (SoC) and Networks-on-Chip (NoC), ·
Parallel and distributed systems and
algorithms, ·
Interconnection networks, ·
Social networks and graph theory. Teaching I have taught graduate courses: ·
Network-based computing ·
Interconnection networks ·
Advanced computer architecture and undergraduate courses: ·
Computer architecture ·
Multicore computing ·
Computer structure and language ·
Computational mathematics ·
Microprocessors Publications Books and Book Chapters 1.
A. Asadinia, H. Sarbazi-Azad, Durable
phase-change memory architectures, in Advances in Computers, Elsevier, Vol.118, 2020,
ISBN: 978-0-12-818754-8. 2.
A. Hurson, H. Sarbazi-Azad (Editor), Dark
silicon and future on-chip systems, in Advances in Computers, Elsevier,
Vol.110, 2018, ISBN: 978-0-128-15358-1. 3.
P. Lotfi-Kamran, H. Sarbazi-Azad, Dark
silicon and the history of computing, Chapter 1, Advances in Computers,
Elsevier, 2018, ISBN: 978-0-128-15358-1. 4.
M. Hoveida, F. Aghaliakbari,
M. Jalili, R. Bashizadeh, M. Arjomand
and H. Sarbazi-Azad, Revisiting processor allocation and application
mapping in future CMPs in dark silicon era, Chapter 2, Advances in
Computers, Elsevier, 2018, ISBN: 978-0-128-15358-1. 5.
M. Modarressi, H. Sarbazi-Azad, Topology
specialization for networks-on-chip in the dark silicon era, Chapter 6,
Advances in Computers, Elsevier, 2018, ISBN: 978-0-128-15358-1. 6.
H. Sarbazi-Azad (Editor), Advances in GPU research and practice,
Elsevier Science, Morgan Kaufmann Publishing Co., 2017, ISBN:
978-0-128-03788-1. 7.
M.H. Samavatian, M. Arjomand,
R. Bashizadeh, H. Sarbazi-Azad, Architecting the
last-level cache for GPUs using STT-RAM nonvolatile memory, Chapter 20,
Advances in GPU research and practice, Elsevier & Morgan Kaufmann, 2017,
ISBN: 978-0-12-803738-6. 8.
P. Zardoshti, F. Khunjush,
H. Sarbazi-Azad, Adaptive sparse matrix representation for efficient
matrix-vector multiplication, Chapter 14 in Advances in GPU research and practice, Elsevier & Morgan
Kaufmann, 2017, ISBN: 978-0-12-803738-6. 9.
A. Hurson, H. Sarbazi-Azad (Editors), Energy efficiency in data centers, in Advances
in Computers, Vol.
100, Elsevier, 2016. 10.
H. Sarbazi-Azad, A. Zomaya (Editors), Large-scale network-centric distributed
systems, Wiley Book Series on Parallel and Distributed Computing, 2013,
ISBN: 978-0-470-93688-7. 11.
R. Jabbarvand,
Mehdi Modarressi, H. Sarbazi-Azad, Fault-tolerant
routing algorithms, Chapter
4 in Networks on-Chip, Springer, 2013. 12.
M. Modarressi, H. Sarbazi-Azad, A reconfigurable on-chip interconnection
network for large multicore systems, Chapter 1 in Large scale network centric distributed systems, By H. Sarbazi-Azad, A. Zomaya
(Editors), Wiley Book Series on Parallel and Distributed Computing,
2013, ISBN: 978-0-470-93688-7. 13.
A. Nayebi, H. Sarbazi-Azad, Mobility effects in wirelss
mobile networks, Chapter 8, Large
scale network centric distributed systems, By H.
Sarbazi-Azad, A. Zomaya (Editors), Wiley
Book Series on Parallel and Distributed Computing, 2013, ISBN:
978-0-470-93688-7. 14.
M. Modarressi, H. Sarbazi-Azad, A high-performance and low-power on-chip
network with reconfigurable topology, Chapter13, Dynamic Reconfigurable Network-on-Chip Design: Innovations for
Computational Processing and Communication, By Jih-Sheng
Shen and Pao-Ann Hsiung (Editors), IGI
Global Publisher, 2010, ISBN: 978-1-61520-807-4. 15.
R. Sabbaghi, M. Modarressi,
H. Sarbazi-Azad, Shuffle-exchange mesh topology for networks-on-chip,
Chapter 5 in Parallel and Distributed
Computing, IN-TECH Publishers, Austria, 2010, ISBN: 978-3-902613-45-5. 16.
R. Sabbaghi, M. Modarressi,
H. Sarbazi-Azad, A novel de Bruijn
based mesh topology for Networks-on-Chip, Chapter 16 in VLSI Design, IN-TECH Publishers,
Austria, 2010, ISBN
978-3-902613-50-9. 17.
H. Hashemi, H. Sarbazi-Azad, Performance modeling and evaluation
of opto-electronic OTIS cubes, Chapter 4, Performance Evaluation of
Parallel, Distributed and Emergent Systems, By G. Min and M. Ould-khaoua (Editors), Nova Science Publishers, 2006,
ISBN: 1-59454-817-X, pp. 83-107. 18.
A. Khonsari, H. Sarbazi-Azad, M. Ould-Khaoua, A performance model of true fully
adaptive routing in hypercubes, Chapter 16, High Performance Computing
Systems and Applications, R. D. Kent, T. W. Sands (Editors), Kluwer
Academic Publishers, 2003, ISBN: 1-4020-7389-5. Editorials in Journals 19.
H. Asadi, P. Ienne, H. Sarbazi-Azad, Architecture of future many
core systems, Elsevier’s
Microprocessors and Microsystems, Vol.46, pp.264-273, 2016. 1.
H. Sarbazi-Azad, N. Bagherzadeh, M. Ebrahimi, M. Daneshtalab,
On-chip parallel and network-based
systems, Editorial notes, Elsevier’s
Computers and Electrical Engineering, Vol.51, No.2, pp.118-120, 2016. 2.
H. Asadi, P. Ienne,
H. Sarbazi-Azad, Emerging memory technologies, IEEE Transactions on
Computers, 65(4):1006-1009, 2016. 3.
H. Sarbazi-Azad, N. Bagherzadeh, G. Jaberipour,
Multicore architectures, Editorial notes, Elsevier’s Journal
of Supercomputing, Vol.71, No.8, pp.2783-2786, 2015. 4.
M. Daneshtalab, H. Sarbazi-Azad, N.
Bagherzadeh, On-chip parallel and
network-based systems, Editorial
notes, Integration: The VLSI Journal, Vol.50, pp.137-138, 2015. 5.
M. Daneshtalab, H. Sarbazi-Azad, N.
Bagherzadeh, On-chip parallel and
network-based systems, Editorial
notes, Computing, Vol.97, No.6, pp.539-541, 2015. 6.
D. Göhringer, H. Sarbazi-Azad, R. Stotzka, Network-on-chips and memories for multicore
architectures, Editorial notes, Elsevier’s
Microprocessors and Microsystems, Vol.38, No.4, pp.253-254, 2014. 7.
H. Sarbazi-Azad, N. Bagherzadeh, Multicore computing systems: architecture, programming tools, and
applications, Editorial notes,
Journal of Computer and System Sciences, Vol.79, No.4, pp.403-405,
2013. 8.
N. Bagherzadeh,H. Sarbazi-Azad, High-performance computer architecture and systems: design and
performance, Editorial notes,
IET Computers and Digital Techniques, Vol.6, No.5, pp.257-258,
2012. 9.
H. Sarbazi-Azad, N. Bagherzadeh, On-chip parallel and network-based systems, Editorial notes, Elsevier’s
Microprocessors and Microsystems, Vol.36, No.7, pp.529-530, 2012. 10. N. Bagherzadeh, H.
Sarbazi-Azad, On-chip Parallel and
Network-based Systems, Editorial
notes, Journal of Systems Architecture, Vol. 57, No.1,
pp. 1-3, 2011. 11.
H. Sarbazi-Azad, A.R. Shahrabi, H. Beigy, Network-based high
performance computing, Editorial
notes, Springer’s Supercomputing journal, Vol. 53, No. 1, pp.
1-4, 2010. 12.
H. Sarbazi-Azad, L. Mackenzie, Advances
in computing systems science and engineering, Editorial notes, Elsevier’s Computers
and Electrical Engineering, Vol. 36, pp. 803-1020, Issue 5, 2010. 13.
H. Sarbazi-Azad, L. Mackenzie, Network-based
computing, Editorial notes,
Elsevier’s Journal of Computer and System Sciences, Vol.73, pp.
1119-1120, 2007. 14.
H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Performance
evaluation of networks for parallel, cluster, and grid computing, Editorial notes, Elsevier’s Parallel
Computing, Vol.32, No. 11 and 12, pp.775-776, 2006. 15.
H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Design and
performance of networks for super-, cluster-, and grid-computing: Part II, Editorial notes, Elsevier’s Journal
of Parallel and Distributed Computing, Vol.65, No.10, pp. 1301-1304,
2005. 16.
H. Sarbazi-Azad, M. Ould-Khaoua, A. Zomaya, Design and
performance of networks for super-, cluster-, and grid-computing: Part I, Editorial notes, Elsevier’s Journal
of Parallel and Distributed Computing, Vol.65, No.9, pp. 1119-1122, 2005. 17.
M. Ould-Khaoua, H. Sarbazi-Azad, M. S. Obaidat, Performance
modeling and evaluation of high-performance parallel and distributed systems, Editorial notes, Elsevier’s Performance
Evaluation: An International Journal, Vol. 60, No.1, 2, 3, and 4, pp.
1-4, 2005. Selected Journal Papers 1.
S. Darabi, E. Yousefzadeh, N. Akbarzadeh, H. Falahati, P. Lotfi-Kamran, M. Sadrosadati, H. Sarbazi-Azad, Quick generation of SSD
performance models using machine learning, IEEE Transactions on
Parallel and Distributed Systems, to appear. 2.
M. Tarihi, S. Azadvar,
A. Tavakkol, H. Asadi, H.
Sarbazi-Azad, Quick generation of SSD performance models using machine
learning, IEEE Transactions on Emerging Topics in Computing, to
appear. 3.
H. Falahati, M. Peyro,
H. Amini, M. Taghian, M. Sadrosadati, P. Lotfi-Kamran,
H. Sarbazi-Azad: Data-aware compression of neural networks. IEEE
Computer Architecture Letterrs, Vol20, No.2,
pp.94-97, 2021. 4.
N. Nematollahi-mahani, M. Sadrosadati, H. Falahati, M. Barkhordar, M.P. Drumond, H.
Sarbazi-Azad, B. Falsafi, Efficient
nearest-neighbor data sharing in GPUs, ACM Transactions on
Architecture and Code Optimization, Vol.18, No.1, pp. 1-26, 2021. 5.
M. Sadrosadati, A. Mirhosseini,
A. Hajiabadi, B. Ehsani,
H. Falahati, H. Sarbazi-Azad, M. Drumond, B. Falsafi, R. Ausavarungnirun, O. Mutlu, Highly concurrent latency-tolerant register
files for GPUs, ACM Transactions on Computer Systems, Vol.37,
No.1, pp.1-36, 2021. 6.
F. Golshan, M. Bakhshalipour, M. Shakernia, A. Ansari, P. Lotfi-Kamran,
H. Sarbazi-Azad, Code harnessing pairwise-correlating data prefetching
with runahead metadata, IEEE Computer
Architecture Letters, to appear. 7.
A. Monemi, F. Khunjush,
M. Palesi, H. Sarbazi-Azad, An
enhanced dynamic weighted incremental technique for QoS support in NoC, ACM Transactions on Parallel Computing,
Vol.7, No.2, pp.9:1-9:31, 2020. 8.
A. Ansari, P. Lotfi-Kamran, H.
Sarbazi-Azad, Code layout optimization for near-ideal instruction cache,
IEEE Computer Architecture Letters, Vol.18, No.2, pp.124-127, 2019. 9.
F. Mireshaghallah, M. Bakhshalipour,
M. Sadrosadati, H. Sarbazi-Azad, Energy-efficient
permanent fault tolerance in hard real-time systems, IEEE Transactions
on Computers, Vol.68, No.10, pp.1539-1545, 2019. 10.
S. Rashidi, M. Jalili, H. Sarbazi-Azad, A survey on PCM lifetime
enhancement schemes, ACM Computing Surveys, Vol.52, No.4, pp.76:1-76:38, 2019. 11.
M. Bakhshalipour, S. Tabaeiaghdaei,
P. Lotfi-Kamran, H. Sarbazi-Azad, Evaluation of
hardware data prefetchers on server processors, ACM Computing Surveys,
Vol.52, No.3, pp.52:1-52:29, 2019. 12.
M. Bakhshalipour, A. Faraji,
S. A. Vakil Ghahani, F. Samandi,
P. Lotfi-Kamran, H. Sarbazi-Azad, Reducing
writebacks through in-cache displacement, ACM Transactions on Design
Automation of Electronic Systems, Vol.24, No.2, pp.16:1-16:21, 2019. 13.
M. Sadrosadati, S. B. Ehsani,
H. Falahati, R. Ausavarungnirun,
A. Tavakkol, M. Abaee, L.
Orosa, Y. Wang, H. Sarbazi-Azad, O. Mutlu, ITAP: Idle-time-aware power management for GPU
execution units, ACM Transactions on Architecture and Code
Optimization, Vol.16, No.1, pp. 3:1-3:26, 2019. 14.
N. Nematollahi, M. Sadrosadati,
H. Falahati, M. Barkhordar,
H. Sarbazi-Azad, Neda: Supporting direct inter-core neighbor data exchange
in GPUs. Computer Architecture Letters, Vol.17, No.2, pp.225-229,
2018. 15.
A. Mirhosseini, M. Sadrosadati,
F. Aghamohammadi, M. Modarressi,
H. Sarbazi-Azad, BARAN: Bimodal adaptive reconfigurable-allocator
network-on-chip, ACM Transactions on Parallel Computing, Vol.5,
No.3, pp.11:1-11:29, 2018. 16.
M. Bakhshalipour, P. Lotfi-Kamran,
A. Mazloumi, F. Samandi,
M. Naderan-Tahan, M. Modarresi,
and H. Sarbazi-Azad, Fast data delivery for many-core processors, IEEE
Transactions on Computers, Vol.67, No.10, pp.1416-1429, 2018. 17.
S. Rashidi, M. Jalili, H. Sarbazi-Azad, Improving MLC PCM performance
through relaxed write and read for intermediate resistance levels, ACM
Transactions on Architecture and Code Optimization, Vol.15, No.1,
pp.12:1-12:31, 2018. 18.
M. Jalili, H. Sarbazi-Azad, Express read in MLC phase change
memories, ACM Transactions on Design Automation of Electronic Systems,
Vol.23, No.3, pp.33:1-33:24, 2018. 19.
M. Naderan, H. Sarbazi-Azad, Domino
cache: an energy efficient data cache for modern applications, ACM
Transactions on Design Automation of Electronic Systems, Vol.23, No.3, pp.31:1-31:23,
2018. 20.
A. Vakil-Ghahani, S. Mahdizadeh-Shahri,
M.-R. Lotfi-Namin, M. Bakhshalipour,
P. Lotfi-Kamran, H. Sarbazi-Azad, Cache
replacement policy based on expected hit count, IEEE Computer
Architecture Letters, Vol.17, No.1, pp.64-67, 2018. 21.
D. Rahmati, H. Sarbazi-Azad, Classified
round robin: a simple prioritized arbitration to equip best effort NoCs with effective hard QoS, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, Vol.37, No.1,
pp.257-269, 2018. 22.
M. Bakhshalipour, P. Lotfi-Kamran,
H. Sarbazi-Azad, An efficient temporal data prefetcher for L1 caches, IEEE
Computer Architecture Letters, Vol.16, No.2, pp.99-102, 2017. 23.
M. Hoveida, F. Agha-aliakbari,
M. Arjomand, H. Sarbazi-Azad, Efficient mapping of
applications for future chip-multiprocessors in dark-silicon era, ACM
Transactions on Design Automation of Electronic Systems, Vol.22, No.4,
pp.70:1-70:26, 2017. 24.
M. Jalili, H. Sarbazi-Azad, Endurance-aware security enhancement
in non-volatile memories using compression and selective encryption, IEEE
Transaction on Computers, Vol.66, No.7, pp.1132-1144, 2017. 25.
M. Hosseinzadeh, M. Arjomand,
H. Sarbazi-Azad, SPCM: The striped phase change memory, ACM Transactions on
Computer Architecture and Code Optimization, 12(4):38-52, 2016. 26.
P. Lotfi-Kamran,
M. Modarressi, H. Sarbazi-Azad, An efficient
hybrid-switched network-on-chip for chip multiprocessors, IEEE
Transaction on Computers, 65(5):1656-1662, 2016. 27.
A. Tavakkol, M. Arjomand,
H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation
strategies in SSDs, ACM Transactions
on Modeling and Performance Evaluation of Computing Systems, Vol.12, No.4, pp.38-52, 2016. 28.
A. Tavakkol, P. Mehrvarzy,
H. Sarbazi-Azad, TBM: Twin block management policy to enhance the
utilization of plane-level parallelism in SSDs, IEEE Computer
Architecture Letters, to appear. (DOI: 10.1109/LCA.2015.2461162) 29.
M. Tarihi, H. Asadi,
M. Arjomand, H. Sarbazi-Azad, A hybrid
non-volatile cache design for solid-state drives using comprehensive I/O
characterization, IEEE Transaction on Computers, Vol.65, No.6,
pp.1678-1691, 2016. 30.
M.R. Jokar, M. Arjomand,
H. Sarbazi-Azad, Sequoia: A high-endurance NVM-based cache architecture,
IEEE Transactions on VLSI Systems, Vol.24, No.3, pp.954-967, 2016. 31. A. Sheshboloki, M. Zarei, H. Sarbazi-Azad, The role of leadership in synchronization of directed complex networks, Journal of Statistical Mechanics Theory and Experiment, No.10, pp.2-17, 2015. 32.
A. Sheshboloki, M. Zarei,
H. Sarbazi-Azad, Are feedback loops destructive to synchronization?, Europhysics
Letters, Vol.111, No.4, pp.3-9, 2015. 33.
M. H. Samavatian,
M. Arjomand, R. Bashizadeh,
H.
Sarbazi-Azad, Architecting the last-level cache for GPUs using STT-RAM
technology, ACM Transactions on Design Automation of Electronic
Systems, Vol.20, No.4, pp.55-73, 2015. 34.
M. Asadinia, M. Arjomand,
H. Sarbazi-Azad, Variable resistance spectrum assignment in phase change
memory systems, IEEE Transactions on VLSI Systems, Vol.23, No.11,
pp.2657-2670, 2015. 35.
M. Asadinia, M. Arjomand,
H. Sarbazi-Azad, Prolonging lifetime of PCM-based main memories through
on-demand page pairing, ACM Transactions on Design Automation of
Electronic Systems, Vol.20, No.2, pp.23-37, 2015. 36.
M. Tarihi, H. Asadi,
H. Sarbazi-Azad, DiskAccel: accelerating
disk-based experiments by representative sampling, ACM Performance
Evaluation Review, Vol.42, No.1, pp.551-552, 2014. 37.
A. Tavakkol, M. Arjomand,
H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation
strategies in SSDs, ACM Performance Evaluation Review, Vol.42,
No.1, pp.551-552, 2014. 38.
A. Tavakkol, M. Arjomand,
H. Sarbazi-Azad, NoSSD: A scalable and
high-performance communication design paradigm for SSDs, IEEE Computer
Architecture Letters, Vol.12, No.1, pp.5-8, 2013. 39.
C. Seiculescu, D. Rahmati, M. Srinivasan,
H. Sarbazi-Azad, L. Benini, G. De Micheli, Designing
best effort networks-on-chip to meet hard latency constraints, ACM
Transactions on Embedded Computing Systems, Vol.12, No.4, pp.108-122,
2013. 40.
D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, H.
Sarbazi-Azad, Computing accurate performance bounds for best effort
networks-on-chip, IEEE Transactions on Computers, Vol.62, No.3,
pp.452-467, 2013. 41.
M. Modarressi, A. Tavakkol,
H. Sarbazi-Azad, Application-aware topology reconfiguration for on-chip
networks, IEEE Transactions on VLSI Systems, Vol.19, No.11, pp.2010-2022
, 2011. 42.
A. Nayebi, G. Karlsson, H. Sarbazi-Azad, Evaluation
and design of beaconing in mobile wireless networks, Ad Hoc Networks, Vol.9, No.3, pp.368-386, 2011. 43.
M. Arjomand,
H. Sarbazi-Azad, Power-performance
analysis of networks-on-chip with arbitrary buffer allocation schemes, IEEE
Transactions on Computer Aided Design for Digital Systems, Vol.29, No.10,
pp.1558-1571, 2010. 44.
M. Modarressi,
A. Tavakkol, H. Sarbazi-Azad, Virtual point-to-point connections for NoCs,
IEEE Transactions on Computer Aided Design for Digital Systems, Vol.29, No.6, pp.855-868, 2010. 45.
R. Moraveji, P. Moinzadeh,
H. Sarbazi-Azad, A. Zomaya, Multi-spanning tree
zone-ordered label-based routing algorithms for irregular networks, IEEE
Transactions on Parallel and Distributed Systems, Vol.22, No.5,
pp.817-832, 2011 . 46.
N. Imani, H. Sarbazi-Azad, A. Zomaya, P. Moinzadeh, Detecting threats in star graphs, IEEE Transactions on Parallel and Distributed
Systems, Vol.20, No.4, pp. 474-483, 2009. 47.
N. Imani, H. Sarbazi-Azad, S.G. Akl, Some
topological properties of star graphs: the surface area and volume,
Discrete Mathematics, Vol.309, pp.560-569, 2009. 48.
H. Sarbazi-Azad, M. Ould-Khaoua, L. M.
Mackenzie, Analytical modelling
of wormhole-routed k-ary n-cubes in the
presence of hot-spot traffic, IEEE Transactions on Computers, Vol. 50, No. 7, pp. 623-634, 2001. 49.
H. Sarbazi-Azad, M. Ould-Khaoua, L.M.
Mackenzie, An accurate analytical model of adaptive wormhole routing in k-ary n-cube interconnection networks, Performance
Evaluation, Vol. 43, No. 2-3, pp. 165-179, 2001. 50.
M. Ould-Khaoua, H. Sarbazi-Azad, An
analytical model of adaptive wormhole routing in hypercubes in the presence
of hotspot traffic, IEEE Transactions on Parallel and Distributed
System, Vol. 12, No.3, pp. 283-292, 2001. Selected Conference Papers 1.
S. Darabi, N. Mahani,
H. Baxishi, E. Yousefzadeh,
M. Sadrossadati, H. Sarbazi-Azad, NURA:
Supporting Non-Uniform Resource Accesses in GPUs, SIGMETRICS 2022,
Mumbai, India, 6-10 June, 2022.. 2.
N. Rohbani, S. Darabi,
H. Sarbazi-Azad, PF-DRAM: A precharge-free DRAM
structure, Proceedings of 48th Intl Symposium on Computer Architecture
(ISCA2021), 14-16 June, 2021, Valencia, Spain. 3.
S. Nabavi-Larimi, B. Salami, O. Unsal, A. Kestelman, H.
Sarbazi-Azad, O. Mutlu, Understanding power
consumption and reliability of high-bandwidth memory with voltage underscaling, Proceedings of Design, Automation and
Test in Europe Conference (DATE2021), 1-5 Feb. 2021, Grenoble, France. 4.
B. Salami, E.B. Onural, I.E. Yuksel, F. Koc, O. Ergin, A.C. Kestelman, O.S.Unsal, H. Sarbazi-Azad, O. Mutlu, An experimental study of reduced-voltage
operation in modern FPGAs for neural network acceleration, Proceedings of
50th IEEE/IFIP Intl. Conference on Dependable Systems and Networks (DSN2020),
29 June-2 July 2020, Valencia, Spain. 5.
A. Ansari, F. Golshan, P. Lotfi-Kamran, H.
Sarbazi-Azad, Divide and conquer instruction cache misses, Proceedings
of 47th Intl Symposium on Computer Architecture (ISCA2020), 30 May-3 June,
2020, Valencia, Spain. 6.
M. Bakhshalipour, M. Shakerinava,
P. Lotfi-Kamran, H. Sarbazi-Azad, Bingo spatial
data prefetcher, The 25th IEEE Symposium on High Performance Computer
Architecture (HPCA2019), 16-20 February 2019, Washington D.C., USA. 7.
M. Sadrosadati, A. Mirhosseini, B.
Ehsani, H. Sarbazi-Azad, M.P. Drumond, B. Falsafi, R. Ausavarungnirun, O. Mutlu, LTRF: enabling high-capacity register
files for GPUs via hardware/software cooperative register prefetching, The 23rd ACM International Conference on
Architectural Support for Programming Languages and Operating Systems
(ASPLOS2018), 24-28 March 2018, Williamsburg, VA, USA. 8.
M. Bakhshalipour, P. Lotfi-Kamran,
H. Sarbazi-Azad, Domino temporal data
prefetcher, The 24th IEEE Symposium on High Performance
Computer Architecture (HPCA2018), 24-28 February 2018, Vienna, Austria. 9.
A. Mirhosseini, M. Sadrosadati, B. Soltani, H.
Sarbazi-Azad, T. Wenisch, BiNoCHS:
Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems, 11th
IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2017, Seoul,
Korea. Best Paper Award! 10. A. Mirhosseini, M. Sadrosadati, B.
Soltani, H. Sarbazi-Azad, T. Wenisch,
Elastic reconfiguration for heterogeneous NoCs with
BiNoCHS, 26th International Conference on
Parallel Architectures and Compilation Techniques (PACT), 2017. 11.
M. Sadrosadati, A.H. Mirhosseini,
S. Roozkhosh, H. Bakhishi,
H. Sarbazi-Azad, Effective cache bank placement for GPUs, International Conference on Design, Automation and Test
in Europe (DATE 2017),
27-31 March 2017, Lausanne, Switzerland. 12.
P. Lotfi-Kamran, M. Modarressi,
H. Sarbazi-Azad, Near-ideal networks-on-chip for servers, The 23rd
IEEE Symposium on High Performance Computer Architecture (HPCA2017), 4-8
February 2017, Austin, TX, USA. 13.
H. Aghilinasab, M. Sadrosadati,
M. Samavatian, H. Sarbazi-Azad,
Reducing power consumption of GPGPUs through
instruction reordering, International
Symposium on Low Power Electronics and Design (ISLPED 2016), 8-10 August
2016, San Francisco, CA, USA. 14.
M. Asadinia, M. Jalili, H. Sarbazi-Azad, BLESS:
a simple and efficient scheme for prolonging PCM lifetime, 53rd Design
Automation Conference (DAC2016), 1-5 June 2016, Austin, TX, USA. 15.
M. Jalili, H. Sarbazi-Azad, Captopril: reducing the pressure of
bit flips on hot locations in non-volatile main memories, International Conference on Design, Automation and Test
in Europe (DATE 2016), 14-18 March 2016, Dresden, Germany. 16.
M. Sadrosadati, A. Mirhosseini, H. Aghilinasab, H.
Sarbazi-Azad, An efficient DVS scheme for
on-chip networks using reconfigurable virtual channel allocators, International
Symposium on Low Power Electronics and Design (ISLPED 2015), 22-24 July 2015,
Rome, Italy. 17.
A. Mirhosseini, M. Sadrosadati, A. Fakhrzadehgany,
M. Modarressi, and H. Sarbazi-Azad, An energy-efficient virtual channel
power-gating mechanism for on-chip networks, International
Conference on Design, Automation and Test in Europe (DATE 2015),
9-13 March 2015, Grenoble, France. 18.
M. Tarihi, H. Asadi,
H. Sarbazi-Azad, DiskAccel: accelerating
disk-based experiments by representative sampling, ACM SIGMETRICS, 15-19
June 2015, Portland, Oregon, USA. 19.
A. Tavakkol, M. Arjomand,
H. Sarbazi-Azad, Design for scalability in enterprise SSDs, The 23rd
International Conference on Parallel Architectures and Compilation Techniques
(PACT2014), 24-27 August 2014, Edmonton, Alberta, Canada. 20.
M. Hoseinzadeh, M. Arjomand,
H. Sarbazi-Azad, Reducing access latency of MLC PCMs, 41st
ACM/IEEE International Symposium on Computer Architecture (ISCA2014), 14-18
June 2014, Minneapolis, MN, USA. 21.
M. Jalili, M. Arjomand, H. Sarbazi-Azad, A
reliable 3D MLC PCM architecture with resistance drift predictor, 44th
Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN2014),
23-26 June 2014, Atlanta, GA, USA. 22.
A. Tavakkol, M. Arjomand,
H. Sarbazi-Azad, Unleashing the potentials of dynamism for page allocation
strategies in SSDs, ACM SIGMETRICS, 16-20 June 2014, Austin, TX, USA. 23.
M. Samavatian, M. Abbasitabar,
M. Arjomand, H. Sarbazi-Azad, Fast and low-power
STT-RAM last level cache for GPGPUs, 51st Design Automation Conference
(DAC2014), 1-5 June 2012, San Francisco, CA, USA. 24.
M. Asadinia, M. Arjomand,
H. Sarbazi-Azad, OD3P: on-demand page paired PCM, 51st Design
Automation Conference (DAC2014), 1-5 June 2012, San Francisco, CA, USA. 25.
M. Arjomand, H. Sarbazi-Azad, A. Jadidi, M. Rezaei, Relaxing writes in non-volatile
processor cache using frequent value locality, 49th Design Automation
Conference (DAC), 3-7 June 2012, San Francisco, CA, USA. 26.
M. Arjomand, A. Jadidi,
A. Shafiee, H. Sarbazi-Azad, A morphable phase
change memory architecture considering frequent zero values,
International Conference on Computer Design (ICCD), 9-12 October 2011,
Amherst, MA, USA. 27.
R. Jabbarvand, M. Modarressi,
H. Sarbazi-Azad, A reconfigurable fault-tolerant routing algorithm to
optimize the network-on-chip performance and latency in presence of
intermittent and permanent faults, International Conference on Computer
Design (ICCD), 9-12 October 2011, Amherst, MA, USA. 28.
A. Shafiee, M. Zolghadr,
M. Arjomand, H. Sarbazi-Azad, Application-aware
deadlock-free oblivious routing based on extended turn-model,
International Conference on Computer-Aided Design (ICCAD),
6-10 November 2011, San Jose, California, USA. 29.
A. Jadidi, M. Arjomand,
H. Sarbazi-Azad, High-endurance and performance-efficient design of hybrid
cache architecture through adaptive line replacement, International
Symposium on Low Power Electronics and Design (ISLPED), 1-3 August 2011,
Fukuoka, Japan. 30.
M. Asadinia, M. Modarressi,
A. Tavakkol, H. Sarbazi-Azad, Supporting
non-contiguous processor allocation in CMPs using virtual point-to-point
links, Design Automation and Test
in Europe (DATE), 14-18 March 2011, Grenoble, France. 31.
M. Modarressi, A. Tavakkol,
H. Sarbazi-Azad, An efficient dynamically reconfigurable on-chip network
architecture, 47th
Design Automation Conference (DAC), 13-18 June 2010, Anaheim,
California. 32.
D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, H.
Sarbazi-Azad, A method for calculating
hard QoS guarantees for networks-on-Chip, IEEE/ACM The International
Conference on Computer-Aided Design (ICCAD), 2-5 November 2009, San Jose, CA,
USA. 33.
H. Sadeghi, H. Sarbazi-Azad, H.R. Zarandi, Power-aware branch target prediction
using a new BTB architecture, The 17th
IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 12-14 October 2009, Florianapolis, Brazil . 34.
M. Modarressi, H. Sarbazi-Azad, A. Tavakol, Performance and power efficient on-chip
communication using adaptive virtual point-to-point connections, ACM/IEEE
Symposium on Networks-on-Chip (NOCS), 10-13 May 2009, San Diego, CA, USA. 35.
M. Arjomand, H. Sarbazi-Azad, A
comprehensive power-performance model for NoCs with
multi-flit channel buffers, 23rd International Conference on
Supercomputing (ICS), 8-12 June 2009, New York, USA. 36.
M. Modarressi, H. Sarbazi-Azad, A hybrid
packet-switched and circuit-switched on-chip network based on
spatial-division multiplexing, Design, Automation and Test in Europe
(DATE), 20-24 April 2009, Nice, France. 37.
M. Modarressi, H. Sarbazi-Azad, A. Tavakol, Virtual point-to-point links in packet
switched NoCs, IEEE International Symposium on
VLSI (IEEE ISVLSI2008),
2008, France. 38.
R. Sabbaghi, H. Sarbazi-Azad, The 2D DBM: an attractive alternative to
the simple 2D mesh topology for on-chip networks, 26th IEEE International Conference
on Computer Design (ICCD), 39.
M. Modarressi, H. Sarbazi-Azad, Power-aware
mapping for reconfigurable NoC architectures,
IEEE International Conference on Computer Design (IEEE ICCD), 7-10 October
2007, Lake Tahoe, CA, USA. 40.
N. Imani, H. Sarbazi-Azad, A. Zomaya, Capturing
an intruder in product networks, 13th Annual IEEE International
Conference on High Performance Computing (IEEE HiPC’2006), December 18-21,
2006, Bangalore, India, pp.193-204. 41.
D. Rahmati, A. Eslami, S. Hessabi, H. Sarbazi-Azad, A performance and power analysis of WK-recursive and
mesh networks for network-on-chips, Proceedings of IEEE International
Conference on Computer Design (ICCD’2006), October 1-3, 2006, San Jose, USA. 42.
H. Hashemi-Najafabadi, H. Sarbazi-Azad, An
accurate combinatorial model for performance prediction of deterministic
wormhole routing in torus multicomputer systems, Proceedings of IEEE
International Conf. on Computer Design (IEEE ICCD'04), Oct. 25 - 29, 2004,
San Jose, CA, USA, pp. 548-553. 43.
H. Hashemi-Najafabadi, H. Sarbazi-Azad,
The effect of adaptivity on the performance of the OTIS-hypercube under
different traffic patterns, Proceedings of IFIP International Conference
on Network and Parallel Computing (IFIP NPC'2004), Lecture Notes in Computer Science, October
18-20, 2004, Wuhan, China, pp. 390-398 . 44.
A. Khonsari, H.
Sarbazi-Azad, M. Ould-Khaoua, Analysis of true fully adaptive routing with
software-based deadlock recovery, Proc. of International
Conference on Parallel Processing (ICPP2001), 3-7 September, 2001, Valencia,
Spain, pp. 393-400. 45.
H. Sarbazi-Azad, M. Ould-Khaoua, L.M.
Mackenzie, S. Akl, Parallel Lagrange
interpolation on the star, Proc. IEEE & ACM Int. Parallel &
Distributed Processing Symposium (IPDPS'2000), IEEE Computer Society Press,
Cancun, Mexico, May 1-5, 2000, pp. 777-782. 46.
H. Sarbazi-Azad, M. Ould-Khaoua, L.M.
Mackenzie, An analytical model of fully-adaptive wormhole-routed k-ary n-cubes in the presence of hot-spot traffic, Proc.
IEEE & ACM Int. Parallel & Distributed Processing Symposium
(IPDPS'2000), IEEE Computer Society Press, Cancun, Mexico, May 1-5, 2000, pp.
605-610. |
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